Intel Aims to Pack a Trillion Transistors into a Chip Package by 2030

As chip packaging technology advances, Intel has set an ambitious goal of incorporating a trillion transistors into a single package by 2030, leveraging their next-generation chip packaging innovations.

Intel has been a trailblazer in the realm of advanced packaging for several decades. Among their notable contributions are technologies such as EMIB (embedded multi-die interconnect bridge) and Foveros. EMIB enables the connection of multiple chips on a single package in a side-by-side configuration, while Foveros facilitates stacking multiple chips on top of each other in a 3D arrangement.

Ann Kelleher, the executive vice president and general manager of Intel’s Technology Development division, highlighted the significance of advanced packaging and heterogeneous integration. She emphasized that these approaches allow for the integration of a significantly larger number of components within a given package and product.

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“As Moore’s Law has been progressing, traditional scaling has been slowing down,” said Ann Kelleher. “But as we start doing advanced packaging and heterogeneous integration, it means we can pack a lot more components into a given package and a given product,” she added.

Intel’s prowess in packaging technology also bolsters its position in Intel Foundry Services (IFS). Mark Gardner, senior director of Foundry Advanced Packaging at IFS, noted that Intel’s reputation as a trusted technology company with a strong track record in both standard and advanced packaging is highly regarded by their Foundry customers. Additionally, Intel’s extensive scale, capacity, and global presence set them apart from many other suppliers in the industry.

Once given little attention in chipmaking, packages are changing how chips are designed and created – and, ultimately, what chips can do, according to the chip major.

​”The world’s most intricate and high-tech package is one you likely never see,” said the company.

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